This invention relates to a plasma processing apparatus such as a plasma etching apparatus used for dry etching semiconductor integrated circuits, and a plasma processing method.
Semiconductor integrated circuits have become more and more miniaturized and complicated to satisfy requirements for higher functions and higher operation speeds. In plasma processing apparatuses for processing such semiconductor integrated circuits, as disclosed in JP-A-2-65131, it has conventionally been known to prevent electrostatic damage of a wafer by disposing a ring having electric conduction around an outer periphery of the wafer.
However, the conventional technology described above is not yet entirely satisfactory for preventing electrostatic damage in gate oxide films the thickness of which has become smaller and in those wafers the diameter of which has become greater such as 12 inches or more. This technology cannot either reduce entirely sufficiently electrostatic damage that changes depending on process conditions varying to large extents.
The plasma etching technologies for processing semiconductor circuits according to the prior art attempt to find out a compatible condition that does not invite damage depending on process parameters but provides good shape processability, and conduct the dry etching process.
However, a process window having high shape processability has become small as the semiconductor devices have become miniaturized and have come to possess a higher aspect ratio while the diameter of the wafers to be processed has become greater. Therefore, it is difficult according to the prior art technologies described above to simultaneously satisfy a process window free from damage and a high processing factor such as a processing rate without their trade-off.
Barns et al U.S. Pat. No. 5,535,507 discloses an electrostatic chuck for supporting a workpiece by electrostatic attraction between the workpiece and an electrode for installing the workpiece, and offsetting etching non-uniformity of the workpiece. However, this reference does not teach or suggest means for preventing a defect due to “charging damage” of the workpiece.
JP-A-8-316212 discloses another technique in which an electrode portion of a wafer mount is divided into a plurality of electrically isolated areas, impedance matching elements are connected to respective areas so as to control the impedances thereof, and alternatively, a recessed portion is provided on the electrode surface of the wafer mount such that the impedances between the wafer and the electrode differ between the center portion and the outer portion of the electrode to make ion energy emitted to the wafer uniform over the entire surface, thereby achieving a uniform plasma process.
As disclosed in JP-A-8-181107, there is known a technique that a surrounding ring formed of ceramic is provided around a lower electrode, a wafer is mounted on the surrounding ring so as to have a space between the wafer and the lower electrode and thereby have an electrostatic capacitance, so that a DC voltage generated in a plasma is distributed into the space, a blocking capacitor and the wafer to prevent occurrence of charging damage to the wafer.
However, both of the techniques do not make reference to the compensation for the charging damage of the workpiece which the present invention intends to solve.